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TDA9106 low cost deflection processor for multisync monitors october 1997 preliminary data 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 gnd sda scl 5v h/hvin hlockout vsyncout test hout vsyncin vfocus ewout vfly vout vdcout vcap v ref vagccap vgnd vblkout hblkout s/g pll1inhib pll2c href hfly hgnd fc2 fc1 c0 r0 pll1f hlockcap hpos xray hfocuscap hfocus v cc gnd houtem houtcol moire 9106-01.eps pin connections shrink42 (plastic package) order code : TDA9106 horizontal . self-adaptative . dual pll concept . 150khz maximum frequency . x-ray protection input . i 2 c controls : horizontal duty-cycle, h-position, free running frequency, frequency generator for burn-in mode vertical . vertical ramp generator . 50 to 165hz agc loop . geometry tracking with v-pos & amp . i 2 c controls : v-amp, v-pos, s-corr, c-corr i 2 c geometry corrections . vertical parabola generator (pincushion, keystone, corner correction, top/bottom corner correction balance) . horizontal dynamic phase (side pin balance & parallelogram) . horizontal and vertical dynamic fo- cus (horizontal focus amplitude, horizontal focus symmetry) general . sync processor . hor. & vert. sync output for mcu . hor. & vert. blanking outputs . 12v supply voltage . 8v reference voltage . hor. & vert. lock unlock outputs . read/write i 2 c interface . horizontal moire or dac output this is advance information on a new product now in development or undergoing evaluation. details are subject to change without notice. description the TDA9106 is a monolithic integrated circuit as- sembled in 42 pins shrunk dual in line plastic pack- age. this ic controls all the functions related to the horizontal and vertical deflection in multimodes or multi-frequency computer display monitors. the internal sync processor, combined with the very powerful geometry correction block are making the TDA9106 suitable for very high performance moni- tors with very few external components. it is particularly well suited for high-end 15" and 17" monitors. combined with st7275 microcontroller family, tda9206 (video preamplifier) and stv942x (on-screen display controller) the TDA9106 allows to built fully i 2 c bus controlled computer display monitors, thus reducing the number of external components to a minimum value. 1/30
pin connections pin name function 1 s/g sync on green input 2 moire moire output 3 pll1 inhib ttl-compatible input for pll1 inhibition 4 pll2c second pll loop filter 5 href horizontal section reference voltage (to filter) 6 hfly horizontal flyback input (positive polarity) 7 hgnd horizontal section ground 8 fc2 vco low threshold filtering capacitor 9 fc1 vco high threshold filtering capacitor 10 c0 horizontal oscillator capacitor 11 r0 horizontal oscillator resistor 12 pll1f first pll loop filter 13 hlockcap first pll lock/unlock time constant capacitor 14 hpos horizontal centering output (to filter) 15 xray x-ray protection input (with internal latch function) 16 hfocuscap horizontal dynamic focus oscillator capacitor 17 hfocus horizontal dynamic focus output 18 v cc supply voltage (12v typ) 19 gnd general ground (related to v cc ) 20 houtem horizontal drive output (internal transistor emitter) 21 houtcol horizontal drive output (int. trans. open collector) 22 hblkout horizontal blanking output (see activation table) 23 vblkout vertical blanking output (see activation table) 24 vgnd vertical section ground 25 vagccap memory capacitor for automatic gain control loop in vertical ramp generator 26 v ref vertical section reference voltage (to filter) 27 vcap vertical sawtooth generator capacitor 28 v dcout vertical position reference voltage output 29 vout vertical ramp output (with frequency independant amplitude and s or c corrections if any) 30 vfly vertical flyback input (positive polarity) 31 ewout east/west pincushion correction parabola output (with corner corrections if any) 32 vfocus vertical dynamic focus output 33 vsyncin ttl-compatible vertical sync input (for separated h&v) 34 test not to be used - test pin 35 vsyncout ttl vertical sync output (extracted vsync in case of s/g or ttl composite hv inputs) 36 hout ttl horizontal sync output (to be used for frequency measurement) 37 hlockout first pll lock/unlock output (5v unlocked - 0v locked) 38 h/hvin ttl-compatible horizontal sync input 39 5v supply voltage (5v typ.) 40 scl i 2 c-clock input 41 sda i 2 c-data input 42 gnd ground (related to 5v) 9106-01.tbl TDA9106 2/30
quick reference data parameter value unit horizontal frequency 15 to 150 khz autosynch frequency (for given r0 and c0) 1 to 4.5 fh horizontal sync polarity input yes polarity detection (on both horizontal and vertical sections) yes ttl composite synch or sync on green yes lock/unlock identification (on both horizontal 1st pll and vertical section) yes i 2 c control for h-position 10 % xray protection yes i 2 c horizontal duty adjust 30 to 60 % i 2 c free running adjustment 0.8 to 1.3 f0 stand-by function yes two polarities h-drive outputs yes supply voltage monitoring yes pll1 inhibition possibility yes blanking outputs (both horizontal and vertical) yes vertical frequency 35 to 200 hz vertical autosync (for 150nf) 50 to 165 hz vertical s-correction yes vertical c-correction yes vertical amplitude adjustment yes vertical position adjustment yes east/west parabola output yes pin cushion correction amplitude adjustment yes keystone adjustment yes corner and corner balance adjustments yes internal dynamic horizontal phase control yes side pin balance amplitude adjustment yes parallelogram adjustment yes tracking of geometric corrections yes reference voltage (both on horizontal and vertical) yes dynamic focus (both horizontal and vertical) yes i 2 c horizontal dynamic focus amplitude adjustment yes i 2 c horizontal dynamic focus keystone adjustment yes type of input sync detection (supplied by 5v digital supply) yes horizontal moir output yes i 2 c controlled h-moir amplitude yes frequency generator for burn-in yes fast i 2 c read/write 400 khz 9106-02.tbl TDA9106 3/30
v ref 1 3 4 5 6 7 8 9 10 16 17 18 19 20 30 36 37 38 11 12 13 14 15 21 22 23 33 35 v cc x-ray 2 moire moire processor 5 bits h-fly vsync amp & keyst 2 x 5 bits hfocus cap hfocus gnd href hgnd vfly hblkout vblkout blanking generator vfly vsync hfly lock sync processor sync input select (2 bits) safety processor lock/unlock identification phase comparator phase shifter h-duty (5 bits) hout buffer phase/frequency comparator h-phase (7 bits) vco safe freq. 2 bits free running 5 bits vamp 7 bits 26 27 28 29 40 24 31 32 25 39 41 42 reset generator i 2 c interface v ref vgnd 5v sda scl gnd v ref s and c correction vertical oscillator ramp generator geometry tracking 6 bits 6 bits vpos 7 bits x 2 7 bits 6 bits key bal 6 bits spin bal 6 bits TDA9106 pll1inhib pll1f hposfilter hlockout hlockcap r0 c0 fc1 fc2 hfly pll2c houtcol houtem v cap v agccap v dcout v out vfocus 34 vsyncout hout s/g test vsyncin h/hvin ewout corner correction (2 x 6 bits) x 2 x 2 x x 2 x h-sawtooth generator 9106-02.eps block diagram TDA9106 4/30
absolute maximum ratings symbol parameter value unit v cc supply voltage (pin 18) 13.5 v v dd supply voltage (pin 39) 5.7 v v in max voltage on pin 6 pins 15, 21, 22, 23 pin 1 pin 4 pins 3, 33,34,37,38,40,41 pin 16 pins 8, 9, 10, 11, 12, 13, 14, 25, 27, 30 1.8 12 3.6 4 5 6 8 v v v v v v v vesd esd susceptibility human body model,100pf discharge through 1.5k w eiaj norm,200pf discharge through 0 w 2 300 kv v t stg storage temperature -40, +150 o c t j junction temperature +150 o c t oper operating temperature 0, +70 o c 9106-03.tbl thermal data symbol parameter value unit r th (j-a) junction-ambient thermal resistance max. 65 o c/w 9106-04.tbl synchro processor operating conditions symbol parameter test conditions min. typ. max. unit hsvr horizontal sync input voltage pin 38 0 5 v mind minimum horizontal input pulses duration pin 38 0.7 m s mduty maximum horizontal input signal duty cycle pin 38 25 % vsvr vertical sync input voltage pin 33 0 5 v vsw minimum vertical sync pulse width pin 33 5 m s vsmd maximum vertical sync input duty cycle pin 33 15 % vextm maximum vertical sync width on ttl h/vcomposite or s/g pins 1, 38 750 m s electrical characteristics (v dd = 5v, t amb = 25 o c) symbol parameter test conditions min. typ. max. unit vsgdc s/g clamped dc level pin 1, i 1 = -1 m a1v isgbias internal diode bias current pin 1, v 1 = 1.6v 10 m a vsgth slicing level (see application design choice) pin 1 0.2 v vinth horizontal and vertical input voltage (pins 33,38) low level high level 2.2 0.8 v v rin horizontal and vertical pull-up resistor pins 33,38 200 k w vout output voltage (pins 35,36,37) low level high level 0 5 v v tfrout falling and rising output cmos buffer pins 35,36,37 cout = 20pf 100 ns vhlock horizontal 1st pll lock output status (pin 37) locked unlocked 0 5 v v voutt extracted vsync integration time (% of th) on h/v composite or s/g pin 35, c0 = 820pf 26 35 % 9106-05.tbl TDA9106 5/30
i 2 c read/write electrical characteristics (v dd = 5v,t amb = 25 o c) symbol parameter test conditions min. typ. max. unit i 2 c processor fscl maximum clock frequency pin 40 400 khz tlow low period of the scl clock pin 40 1.3 m s thigh high period of the scl clock pin 40 0.6 m s vinth sda and scl input threshold pins 40,41 2.2 v vack acknowledge output voltage on sda input with 3ma pin 41 0.4 v see also i 2 c table control and i2c sub address control horizontal section operating conditions symbol parameter test conditions min. typ. max. unit vco r 0(min.) minimum oscillator resistor pin 11 6 k w c 0(min.) minimum oscillator capacitor pin 10 390 pf f (max.) maximum oscillator frequency 150 khz output section i6m maximum input peak current pin 6 2 ma hoi1 hoi2 horizontal drive output maximum current pin 20 pin 21 sourced current sunk current 20 20 ma ma electrical characteristics (v cc = 12v, t amb = 25 o c) symbol parameter test conditions min. typ. max. unit supply and reference voltages v cc supply voltage pin 18 10.8 12 13.2 v v dd supply voltage pin 39 4.5 5 5.5 v i cc supply current pin 18 50 ma i dd supply current pin 39 5 ma v ref-h horizontal reference voltage pin 5, i = 5ma 7.4 8 8.6 v v ref-v vertical reference voltage pin 5, i = 5ma 7.4 8 8.6 v i ref-h max. sourced current on v ref-h pin 5 5 ma i ref-v max. sourced current on v ref-v pin 26 5 ma 9106-05.tbl TDA9106 6/30
horizontal section (continued) electrical characteristics (v cc = 12v, t amb = 25 o c) (continued) symbol parameter test conditions min. typ. max. unit 1st pll section hpolt polarity integration delay 0.75 ms v vco vco control voltage (pin12) v ref-h = 8v f 0 f h (max.) v ref-h / 6 6.2 v v vcog vco gain (pin 12) r 0 = 6.49k w , c 0 = 820pf, df/dv = 1/11r 0 c 0 17 khz/v hph horizontal phase adjustment % of horizontal period 10 % hphmin hphtyp hphmax horizontal phase decoupling output minimum value typical value maximum value sub-address 01, pin 14 byte x1111111 byte x1000000 byte x0000000 2.8 3.4 4.0 v v v f 0 free running frequency r 0 = 6.49k w , c 0 = 820pf, f 0 = 0.97/8r 0 c 0 22.3 khz df0/dt free running frequency thermal drift (no drift on external components) -150 ppm/c f 0 (min.) f 0 (max.) free running frequency adjustment minimum value maximum value sub-address 02 byte xxx11111 byte xxx00000 0.8 1.3 f0 f0 cr pll1 capture range r 0 = 6.49k w , c 0 = 820pf, from f 0 +0.5khz to 4.5f 0 f h (min.) f h (max.) 100 23.5 khz khz pllinh pll1 inhibition (pin3) typ threshold = 1.6v pll on pll off 2 0.8 v v sff safe forced frequency sf1 byte 11xxxxxx sf2 byte 10xxxxxx sub-address 02 2f0 3f0 fc1 fc2 vco sawtooth level high fc1=(4.v ref-h )/5 low fc2=(v ref-h )/5 pin 9 to filter pin 8 to filter 6.4 1.6 v v 2nd pll section and horizontal output section fbth flyback input threshold voltage (pin 6) 0.65 0.75 v hjit horizontal jitter (see pins 8-9 filtering) tbd ppm hdmin hdmax horizontal drive output duty-cycle (pin 20 or 21) (see note 1) low level high level (see note 2) sub-address 00 byte xxx11111 byte xxx00000 30 60 % % xrayth x-ray protection input threshold voltage pin 15 8 v vphi2 internal clamping levels on 2nd pll loop filter (pin 4) low level high level 1.6 4.0 v v vscinh threshold voltage to stop h-out,v-out when v cc < vscinh pin 18 7.5 v ihblk maximum horizontal blanking output current i 22 10 ma vhblk horizontal blanking output low level (blanking on) v 22 with i 22 = 10ma 0.25 0.5 v hdvd hdem horizontal drive output low level (pin 20 to gnd) high level (pin 21 to v cc =12v) v 21 -v 20 , i out = 20ma v 20 , i out = 20ma 9.5 1.1 10 1.7 v v notes : 1. duty cycle is the ratio of power transistor off time to period. power transistor is off when output transistor is off. 2. initial condition for safe operation start up (max. duty cycle). 9106-05.tbl TDA9106 7/30
horizontal section (continued) electrical characteristics (v cc = 12v, t amb = 25 o c) (continued) symbol parameter test conditions min. typ. max. unit horizontal dynamic focus section hdfst horizontal dynamic focus sawtooth minimum level maximum level hfocuscap = c 0 = 820pf, f h = 90khz, pin 16 2 4.7 v v hdfdis horizontal dynamic focus sawtooth discharge width driven by hfly 500 ns hdfdc bottom dc output level r load = 10k w , pin 17 2 v tdhdf dc output voltage thermal drift 200 ppm/c hdfamp horizontal dynamic focus amplitude min byte xxx11111 typ byte xxx10000 max byte xxx00000 sub-address 03, pin 17, f h = 90khz, keystone typ 1 1.5 3 v pp v pp v pp hdfkeyst horizontal dynamic focus keystone min a/b byte xxx11111 typ byte xxx10000 max a/b byte xxx00000 sub-address 04, f h = 90khz, typ amp b/a a/b a/b 3.5 1.0 3.5 moire output r moire minimum output resistor pin 2 2 k w v moire output voltage (moire off), subaddress 0f pin 2, r moire = 2k w byte 0xx00000 byte 0xx10000 byte 0xx11111 0.2 1.1 2.0 v v v 9106-05.tbl TDA9106 8/30
vertical section operating conditions symbol parameter test conditions min. typ. max. unit outputs section vewm maximum ew output voltage pin 31 6.5 v vewm minimum ew output voltage pin 31 1.8 v vdfm minimum vertical dynamic focus output voltage pin 32 1.8 v r load minimum load for less than 1% vertical amplitude drift pin 25 65 m w electrical characteristics (v cc = 12v, t amb = 25 o c) symbol parameter test conditions min. typ. max. unit vertical ramp section vrb voltage at ramp bottom point v ref-v =8v, pin 27 2 v vrt voltage at ramp top point (with sync) v ref-v pin 27 5 v vrtf voltage at ramp top point (without sync) pin 27 vrt- 0.1 v vstd vertical sawtooth discharge time duration (pin 27) with 150nf cap 80 m s vfrf vertical free running frequency (see notes 3 & 4) c osc (pin 27) = 150nf measured on pin27, 100 hz asfr auto-sync frequency c 27 = 150nf 5% see note 5 50 165 hz rafd ramp amplitude drift versus frequency at maximum vertical amplitude c 27 = 150nf 50hz < f and f < 165hz 200 tbd ppm/hz rlin ramp linearity on pin 27 (see notes 3 & 4) 2.5 < v 27 and v 27 < 4.5v 0.5 % vpos vertical position adjustment voltage (pin28) sub address 06 byte x0000000 byte x1000000 byte x1111111 3.65 3.2 3.5 3.8 3.3 v v v i vpos max current on vertical position output pin 28 2ma vor vertical output voltage (peak-to-peak on pin 29) sub address 05 byte x0000000 byte x1000000 byte x1111111 3.5 2.25 3 3.75 2.5 v v v voutdc dc voltage on vertical output see note 6, pin 29 3.5 v voi vertical output maximum current (pin29) 5ma dvs max vertical s-correction amplitude x0xxxxxx inhibits s-corr x1111111 gives max s-corr subaddress 07 d v/v pp at t/4 d v/v pp at 3t/4 -4 +4 % % ccorr vertical c-corr amplitude x0xxxxxx inhibits c-corr subaddress 08 byte x1000000 byte x1100000 byte x1111111 -3 0 3 % % % vflyth vertical flyback threshold pin 30 1 v vflyinh inhibition of vertical flyback input see note 7, pin 30 7.5 v notes : 3. with register 07 at byte x0xxxxxx (vertical s-correction control) then the s correction is inhibited, consequently the sawtoo th has a linear shape. 4. with register 08 at byte x0xxxxxx (vertical c - correction control) then the c correction is inhibited, consequently the sawt ooth has a linear shape. 5. it is the frequency range for which the vertical oscillator w ill automatically synchronize, using a single capacitor value on pin 27 and with a constant ramp amplitude. 6. v outdc = (7/16).v ref-v . typically 3.5v for vertical reference voltage typical value (8v). 7. when pin 30 ( v ref-v ) - 0.5v, vfly input is inhibited and vertical blanking on vertical blanking output is replaced by vertical sawtooth discharge time. 9106-05.tbl TDA9106 9/30
vertical section (continued) electrical characteristics (v cc = 12v, t amb = 25 o c) (continued) symbol parameter test conditions min. typ. max. unit east/west function ew dc dc output voltage with typ vpos,keystone, corner and corner balance inhibited pin 31, see figure 1 2.5 v tdew dc dc output voltage thermal drift see note 8 100 ppm/c ewpara parabola amplitude with vamp max, v-pos typ, keystone, corner and corner balance inhibited subaddress 09 byte 1x111111 byte 1x100000 byte 1x000000 2.6 1.4 0 v v v ewtrack parabola amplitude function of v-amp control (tracking between v-amp and e/w) with typ vpos, keystone, corner and corner balance inhibited, ew typ amplitude (see note 9) subaddress 05 byte 10000000 byte 11000000 byte 11111111 0.45 0.8 1.4 v v v keyadj keystone adjustment capability with typ vpos, corner and corner balance inhibited, ew inhibited and vertical amplitude max (see note 9 and figure 4) subaddress 0a byte 10000000 byte 11111111 1 1 v pp v pp keytrack in trinsic keystone function of v-pos control (tracking between v-pos and ew) with corner and corner balance inhibited, ew max amplitude and vertical amplitude max (see note 9) a/b ratio b/a ratio subaddress 06 byte x0000000 byte x1111111 0.5 0.5 corner max max corner correction amplitude with vamp max, v-pos typ, ewamp, keystone and corner balance inhibited (see note 9) subaddress 0b d ewout at t/6, 5t/6 byte x1111111 byte x1000000 +0.2 -0.2 v v corner balmax max corner balance correction amplitude with vamp max, v-pos typ, ewamp, keystone and corner inhibited subaddress 0c (see note 9) byte 01111111 d ewout at t/4 d ewout at 3t/4 +0.2 -0.2 v v byte 01000000 d ewout at t/4 d ewout at 3t/4 -0.2 +0.2 v v internal horizontal dynamic phase control function spbpara side pin balance parabola amplitude (figure 2) with vamp max, v-pos typ and parallelogram inhibited (see notes 9 & 10) subaddress 0d byte x1111111 byte x1000000 +2.8 -2.8 %th %th spbtrack side pin balance parabola amplitude function of vamp control (tracking between vamp and spb) with spb max, v-pos typ and parallelogram inhibited (see notes 9 & 10) subaddress 05 byte 10000000 byte 11000000 byte 11111111 1.0 1.8 2.8 %th %th %th paradj parallelogram adjustment capability with vamp max, v-pos typ and spb inhibited (see notes 9, 10 & 11) subaddress 0e byte x1111111 byte x1000000 +2.8 -2.8 %th %th partrack intrinsic parallelogram function of vpos control (tracking between v-pos and dhpc) with vamp max, spb max and parallelogram inhibited (see notes 9 & 10) a/b ratio b/a ratio subaddress 06 byte x0000000 byte x1111111 0.5 0.5 notes : 8. these parameters are not tested on each unit. they are measured during our internal qualification 9. refers to notes 3 & 4 from last section. 10.th is the horizontal pll period duration. 11.figure 2 is representing effect of dynamic horizontal phase control. 9106-05.tbl TDA9106 10/30
vertical section ( continued) electrical characteristics (v cc = 12v, t amb = 25 o c) (continued) symbol parameter test conditions min. typ. max. unit vertical dynamic focus function vdf dc dc output voltage with v-pos typ see figure 3 6 v tdvdf dc dc output voltage thermal drift see note 12 100 ppm/c vdfamp parabola amplitude function of vamp (tracking between vamp and vdf) with v-pos typ (see figure 3) (see note 13) subaddress 05 byte 10000000 byte 11000000 byte 11111111 0.9 1.6 2.5 v v v vdfkey parabola assymetry function of vpos control (tracking between v-pos and vdf) with vamp max. (see note 13) subaddress 06 byte x0000000 byte x1111111 0.5 0.5 notes : 12. parameter not tested on each unit but measured during our internal qualification procedure including batches coming from cor ners of our process and also temperature characterization 13. s and c corrections are inhibited so the output sawtooth has a linear shape. 9106-05.tbl dhpc dc a b spb para 9106-04.eps figure 2 : dynamic horizontal phase control output vdf dc a b vdf amp 9106-05.eps figure 3 : vertical dynamic focus function ew dc a b ew para 9106-03.eps figure 1 : e/w output keyadj 9106-06.eps figure 4 : keystone effect on e/w output (pcc inhibited) TDA9106 11/30
typical vertical output waveforms function sub address pin byte specification picture image vertical size 05 29 10000000 11111111 vertical position dc control 06 28 x0000000 x1000000 x1111111 3.2v 3.5v 3.8v vertical s linearity 07 29 x0xxxxxx inhibited x1111111 vertical c linearity 08 29 x1000000 x1111111 9106-06.tbl / 9106-07.eps to 9106-13.eps 2.25v 3.75v v pp d v d v v pp = 4% v pp d v d v v pp = 3% d v v pp d v v pp = 3% TDA9106 12/30
geometry output waveforms function sub address pin byte specification picture image trapezoid control 0a 31 ewamp typ. 10000000 11111111 pin cushion control 09 31 keystone inhibited 1x000000 1x111111 parrallelogram control 0e internal spb inhibited x1000000 x1111111 side pin balance control 0d internal parallelogram inhibited x10000000 x1111111 vertical dynamic focus 32 9106-07.tbl / 9106-14.eps to 9106-22.eps 3.75v 2.75v 2.5v 3.75v 2.75v 2.5v 0v 2.5v 2.5v 2.8% th 3.7v 3.7v 2.8% th 2.8% th 3.7v 2.8% th 3.7v 2.5v 6v TDA9106 13/30
function sub address pin byte specification picture image corner control 0b 31 ewamp typ. x1111111 01000000 corner balance control 0c 31 ewamp typ. 10000000 11111111 note : the specification of output voltage is indicated on 3.75v pp vertical sawtooth output condition.the output voltage depends on vertical sawtooth output voltage. 9106-07.tbl / 9106-23.eps to 9106-30.eps geometry output waveforms (continued) without corner corner effect corner effect corner effect corner effect TDA9106 14/30
i 2 c bus address table sub address definition slave address (8c) : write mode d8 d7 d6 d5 d4 d3 d2 d1 0xxxx0000horizontal drive sele ction / horizontal duty cycle 1xxxx0001horizontal po sition 2xxxx0010safety fr equency / free running frequency 3xxxx0011synchro priority / horizontal focus amplitude 4xxxx0100refresh / ho rizontal focus keystone 5xxxx0101ve rtical ramp amplitude 6xxxx0110ve rtical position adjustment 7xxxx0111s corre ction 8xxxx1000c corre ction 9xxxx1001e/w amplitude axxxx1010e/w keystone bxxxx1011cbow corner cxxxx1100spin corner dxxxx1101side pin balance exxxx1110parallelogram fxxxx1111moire control amp litude slave address (8d) : read mode d8 d7 d6 d5 d4 d3 d2 d1 0xxxx0000synchro and polarity detection TDA9106 15/30
table : register map d8 d7 d6 d5 d4 d3 d2 d1 write mode 00 blk sel 1, blk [0] hdrive 0, off [1], on horizontal duty cycle [0] [0] [0] [0] [0] 01 xray 1, reset [0] horizontal phase adjustment [1] [0] [0] [0] [0] [0] [0] 02 safety frequency free running frequency 1, on [0], off 1, f0 x 2 [0], f0 x 3 [0] [0] [0] [0] [0] 03 sync priority horizontal focus amplitude 0, vextr [1], vin 0, s/g [1], h/v [1] [0] [0] [0] [0] 04 detect refresh [0], off horizontal focus keystone [1] [0] [0] [0] [0] 05 vramp 0, off [1], on vertical ramp amplitude adjustment [1] [0] [0] [0] [0] [0] [0] 06 vertical position adjustment [1] [0] [0] [0] [0] [0] [0] 07 s select 1, on [0] s correction [1] [0] [0] [0] [0] [0] 08 c select 1, on [0] c correction [1] [0] [0] [0] [0] [0] 09 ew sel 0, off [1] east/west amplitude [1] [0] [0] [0] [0] [0] 0a ew key 0, off [1] east/west keystone [1] [0] [0] [0] [0] [0] [0] 0b test h 1, on [0], off cbow sel 1, on [0] cbow corner [1] [0] [0] [0] [0] [0] 0c test v 1, on [0], off spin sel 1, on [0] spin corner [1] [0] [0] [0] [0] [0] 0d spb sel 0, off [1] side pin balance [1] [0] [0] [0] [0] [0] 0e parallelo 0, off [1] parallelogram [1] [0] [0] [0] [0] [0] 0f moire 1, on [0], off moire control [0] [0] [0] [0] [0] read mode 00 hlock 0, on [1], no vlock 0, on [1], no xray 1, on [0], off polarity detection synchro detection h/v pol [1], negative v pol [1], negative vext det [0], no det h det [0], no det v det [0], no det [ ] initial value i 2 c bus address table (continued) TDA9106 16/30
operating description i - general considerations i.1 - power supply the typical values of the power supply voltages v cc and v dd are respectively 12v and 5v. perfect operation is obtained if v cc and v dd are maintened in the limits : 10.8 to 13.2v and 4.5 to 5.5v. in order to avoid erratic operation of the circuit during transient phase of v cc switching on, or switching off, the value of v cc is monitored and the outputs of the circuit are inhibited if v cc is less than 7.5v typically. in the same manner,v dd is monitored and internal set-up is made until v dd reaches 4v (see i 2 c control table for power on reset). in order to have a very good power supply rejection, the circuit is internally powered by several internal voltage references (the unique typical value of which is 8v). two of these voltage references are externally accessible, one for the vertical part and one for the horizontal one. if needed, these voltage references can be used (until load is less than 5ma).furthermore it is necessary to filter the a.m. voltage references by the use of external capacitor connected to ground, in order to minimize the noise and consequently the jitter on vertical and hori- zontal output signals. i.2 - i 2 c control TDA9106 belongs to the i 2 c controlled device fam- ily, instead of being controlled by dc voltages on dedicated control pins, each adjustment can be realized through the i 2 c interface. the i 2 c bus is a serial bus with a clock and a data input. the general function and the bus protocol are specified in the philips-bus data sheets. the interface (data and clock) is ttl-level com- patible. the internal threshold level of the input comparator is 2.2v (when v dd is 5v). spikes of up to 50ns are filtered by an integrator and maximum clock speed is limited to 400khz. the data line (sda) can be used in a bidirectional way that means in read-mode the ic clocks out a reply information (1 byte) to the micro-processor. the bus protocol prescribes always a full-byte transmission. the first byte after the start condition is used to transmit the ic-address(7 bits-8c) and the read/write bit (0 write - 1 read). i.3 - write mode in write mode the second byte sent contains the subaddress of the selected function to adjust (or controls to affect) and the third byte the correspond- ing data byte.it is possible to send more than one data byte to the ic. if after the third byte no stop or start condition is detected, the circuit increments automatically the momentary subaddress in the subaddress counter by one (auto-increment mode). so it is possible to transmit immediately the next data bytes without sending the ic address or subaddress. it can be useful so as to reinitialize the whole controls very quickly (flash manner). this procedure can be finished by a stop condition. the circuit has 16 adjustment capabilities: 3 for horizontal part, 4 for vertical one, 2 for e/w correc- tion, 2 for original corner correction, 2 for the dynamic horizontal phase control,1 for moire op- tion and 2 for horizontal dynamic focus. 20 bits are also dedicated to several controls (on/off, horizontal safety frequency, synchro priority, detection refresh and xray reset). i.4 - read mode during read mode the second byte transmits the reply information. the reply byte contains horizontal and vertical lock/unlock status, xray activated or not, the hori- zontal and vertical polarity detection. it also con- tains synchro detection status that is useful for m p to assign sync priority. a stop condition always stops all activities of the bus decoder and switches the data and the clock line (sda and scl) to high impedance. see i 2 c subaddress and control tables. i.5 - synchro processor the internal sync processor allows the TDA9106 to accept any kind of input synchro signals : - separated horizontal & vertical ttl-compatible sync signals, - composite horizontal &vertical ttl-compatible sync signals, - sync on green or composite video signal. TDA9106 17/30
i.6 - sync identification status TDA9106 is able to feed back to the mcu (thanks to i 2 c) the sync input status (sync identification) so that the mcu can choose sync priority through i 2 c. as extracted vertical sync pulse is performed when choice already occured and when 12v is supplied, we recommend to use the device as following :(that means that even in power management mode the ic is able to inform mcu on detected synchro signals due to its 5v supply). first, refresh synchro detection by i 2 c. then check the status of h/v det and vdet by i 2 c read. sync priority choice should be : table 1 : sync priority choice h/v det v det sync priority subaddress 03 comment d8 d7 synchro type yes yes 1 1 separated h & v yes no 0 1 composite ttl h&v no no 0 0 sync on green of course, when choice is done, one can refresh the synchro detections and verify that extracted vsync is present and that no synchro type change occured. synchro processor is also giving synchro polarity information. i.7 - ic status the ic can inform the mcu either the 1st horizontal pll or vertical section are locked or not, and if xray has been activated. this last status permits to the mcu : - reset the xray internal latch decreasing the v cc supply - directly reset throw the i 2 c interface. operating description (continued) i.8 - synchro inputs both h/hvin and vsyncin inputs are ttl compat- ible trigger with hysterisis to avoid erratic detection. it includes pull up resistor to v dd . vertical sync extractor is included for composite sync or composite video.application engineer must adapt resistor r and capacitor c dedicated to its application. 1 s/g rc 1k w i ref (typ.) = 10 m a 1.6v TDA9106 9106-31.eps figure 5 resistor r is fixed by detection threshold wanted : r < (v threshold / i ref ) then c is determined by maximum pulse width to detect (in general, vertical sync width) : rc > (max pulse width) i.9 - synchro processor outputs synchro processor delivers on 3 ttl-compatible cmos outputs the following signals : - hout as follow : sync mode hout mode hout polarity separated horizontal same as input ttl composite ttl composite same as input s/g composite negative - vsyncout is either vertical extracted pulse output or vsyncin input. it keeps the input polarity. - hlockout is the horizontal 1st pll status : 0v when locked. it permits mcu to adjust free running frequency and optimizes the ic performance. TDA9106 18/30
ii - horizontal part ii.1 - internal input conditions horizontal part is internally fed by synchro proces- sor with a digital signal. corresponding to horizontal synchro pulses or to ttl composite input. concerning the duty cycle of the input signal, the following signals (positive or negative) may be applied to the circuit. using internal integration, both signals are recog- nized on condition that z/t < 25%. synchronization occurs on the leading edge of the internal sync signal. the minimum value of z is 0.7 m s. operating description (continued) z t z 9106-32.eps figure 6 an other integration is able to extract vertical pulse of composite synchro if duty cycle is more than 25% (typically d = 35%). dd c tramext 9106-33.eps figure 7 the last feature performed is the equalizing pulses removing to avoid parasitic pulses on phase com- parator input which is intolerent to wrong or missing pulse. ii.2 - pll1 the pll1 is composed of a phase comparator, an external filter and a voltage controlled oscillator (vco). the phase comparator is a phase frequency type designed in cmos technology. this kind of phase detector avoids locking on false frequencies. it is followed by a charge pump, composed of two current sources sunk and sourced (i = 1ma typ. when locked, i = 140 m a when unlocked). this difference between lock/unlock permits a smooth catching of horizontal frequency by pll1. this effect is reinforced by an internal original slow down system when pll1 is locked avoiding horizontal too fast frequency change. the dynamic behaviour of the pll is fixed by an external filter which integrates the current of the charge pump. a crc filter is generally used (see figure 8). pll1 is internally inhibited during extracted vertical sync (if any) to avoid taking in account missing pulses or wrong pulses on phase comparator.the inhibition results from the opening of a switch lo- cated between the charge pump and the filter (see figure 9). for particular synchro type, mcu can drive pin 3 to high level (ttl compatible input) to inhibit pll1. it can also be used to avoid pll1 locking on synchro inputs if a dangerous mode is detected by the mcu. the vco uses an external rc network. it delivers a linear sawtooth obtained by charge and dis- charge of the capacitor, by a current proportionnal to the current in the resistor. typical thresholds of sawtooth are 1.6v and 6.4v. these two levels are accessible to be filtered as on figure 10 to improve jitter. the control voltage of the vco is typically com- prised between 1.33v and 6v (see figure 10). the theorical frequency range of this vco is in the ratio 1 to 4.5, the effective frequency range has to be smaller 1 to 4.2 due to clamp intervention on filter lowest value. to avoid spread of external compo- nents and the circuit itself, it is possible to adjust free running frequency through i 2 c. this adjust- ment can be made automatically on the manufac- turing line without manual operation by using hlock/unlock information. the adjustment range is 0.8 to 1.3 f0 (where 1.3 f0 is the free running frequency at power on reset). the synchro frequency has to be always higher than the free running frequency. as an example for a synchro range from 24khz to 100khz, the sug- gested free running frequency is 23khz. 12 pll1f 9106-34.eps figure 8 TDA9106 19/30
11 12 loop filter r0 1.6v 6.4v 10 c0 6.4v 1.6v 0 0.875t t rs flip flop (1.3v < v < 6v) 12 i 0 2 4 i 0 i 0 (0.80 < a < 1.30) a i 2 c free running adjustment 9 8 47nf 47nf 9106-36.eps figure 10 : details of vco lockdet 13 h-lockcap comp1 sync processor 38 h/hvin high charge pump low pll inhibition vco 3 pll1inhib 12 11 10 pll1f r0 c0 phase adjust e2 14 h-pos i 2 c hpos adj. osc tramext tramext smfe * lock/unlock status 33 vsyncin 1 s/g * smfe : safety frequency mode enable 9106-35.eps figure 9 : pll1 block diagram operating description (continued) an other feature is the capability for mcu to force horizontal frequency through i 2 c to 2xf0 or 3xf0 (for burn in mode or safety requirement).in this case, inhibition switch is opened leaving pll1 free but voltage on pll1 filter is forced to 2.66v for 2xf0 or 4.0v for 3xf0. the pll1 ensures the coincidence between the leading edge of the synchro signal and a phase reference obtained by comparison between the sawtooth of the vco and an internal dc voltage i 2 c adjustable between 2.8v and 4.0v (corre- sponding to 10%) (see figure 11). this voltage has to be filtered on pin 14 so as to optimize jitter. the TDA9106 also includes a lock/unlock identi- fication block which senses in real time wheither pll1 is locked on the incoming horizontal sync signal or not. the resulting information is available on hlockout (see synchro processor). the block function is described in figure 12. the nor1 gate is receiving the phase comparator output pulses (which also drive the charge pump). when pll1 is locked, on point a there is a very small negative pulse (about 100ns) at each hori- zontal cycle, so after rc filter, there is a high level on pin 13 which forces hlockout to low level. hys- terisis comparator detects locking when pin 13 is reaching 6.5v and unlocking when pin 13 is de- creasing to 6.0v. h osc sawtooth phase ref1 h synchro 1.6v vb 6.4v 2.8vTDA9106 20/30
20k w 220nf 13 from phase comparator nor1 a 6.5v b h-lock cap 37 hlockout 6v 5v 9106-38.eps figure 12 : lock/unlock block diagram operating description (continued) when pll1 is unlocked, the 100ns negative pulse on a becomes much larger and consequently the average level on pin 13 decreases. it forces hlock- out to go high. the pin 13 status is approximately the following : - near 0v when there is no h-sync - between 0 and 4v with h-sync frequency differ- ent from vco - between 4 to 8 v when vco frequency reaches h-sync one (but not already in phase) - near 8v when pll1 is locked. it is important to notice that pin 13 is not an output pin but is only used for filtering purpose (see figure 12). the lock/unlock information is also available throw i 2 c read. ii.3 - pll2 the pll2 ensures a constant position of the shaped flyback signal in comparion with the saw- tooth of the vco (figure 13). h osc sawtooth h drive 1.6v 4.0v 6.4v 7/8t h 1/8t h ts duty cycle internally shaped flyback flyback 9106-39.eps the duty cycle of h-drive is adjustable between 30% and 60%. figure 13 : pll2 timing diagram 20k w q1 gnd 0v 6 hfly 400 w 9106-40.eps figure 14 : flyback input electrical diagram the phase comparator of pll2 (phase type com- parator) is followed by a charge pump with 0.5ma (typ.) output current. the flyback input is composed of an npn transis- tor. this input must be current driven. the maxi- mum recommanded input current is 2ma (see figure 14). the duty cycle is adjustable through i 2 c from 30% to 60%. for start up safe operation, initial duty cycle (after power on reset) is 60% so as to avoid too long conduction of bu transistor. maximum storage time is about 43.75% - (tfly/2.th). typically, tfly/th is around 20% that means ts max is around 33.75%. ii.4 - output section the h-drive signal is transmitted to the output through a shaping block ensuring ts and i 2 c ad- justable duty cycle. in order to secure scanning power part operation, the output is inhibited in the following circumstances : -v cc too low - xray protection activated - during horizontal flyback -i 2 c bit control (voluntary inhibition by mcu). the output stage is composed of a npn darlington bipolar transistor. both the collector and the emittor are accessible (see figure 16). the output darlington is in off-state when the power scanning transistor is also in off-state. TDA9106 21/30
20 21 h-drive v cc 20 21 h-drive v cc 9106-41.eps figure 16 : output stage simplified diagram, showing the two possibilities of connection the maximum output current is 20ma, and the corresponding voltage drop of the output darlington is 1.1v typically. it is evident that the power scanning transistor cannot be directly driven by the integrated circuit. logic block horizontal output inhibition vertical output inhibition vertical blanking output s r q horizontal flyback 0.7v xray protection horizontal blanking output v cc checking v cc v cc off or i 2 c reset xray ref vertical flyback vertical sync vertical sawtooth retrace vertical unlock i 2 c ramp on/off i 2 c drive on/off i 2 c blanking i 2 c ramp on/off i 2 c sfme horizontal unlock horizontal free running detection vertical free running status 9106-42.eps figure 17 : safety functions block diagram operating description (continued) an interface has to be designed between the circuit and the power transistor which can be of bipolar or mos type. ii.5 - x-ray protection the activation of the x-ray protection is obtained by application of a high level on the x-ray input (pin 15 > 8v). the consequencies of x-ray protec- tion are : - inhibition of h-drive output - activation of horizontal blanking output. - activation of vertical blanking output. the reset of this protection is obtained either by v cc switch off or i 2 c reset by mcu (see figure 17). ii.6 - horizontal dynamic focus TDA9106 delivers an horizontal parabola wave form on pin 17. this parabola is performed from a sawtooth in phase with flyback pulse.this sawtooth is present on pin 16 where the horizontal focus capacitor is the same as c0 to obtain a controlled amplitude (from 2 to 4.7v typically). symmetry (keystone) and amplitude are i 2 c adjust- able (see figure 18).this signal has to be con- nected to the crt focusing grids and mixed with vertical dynamic focus. TDA9106 22/30
operating description (continued) horizontal flyback internal trigged horizontal flyback horizontal focus cap sawtooth horizontal dynamic focus parabola output 4.7v 2v 2v 400ns moire output 9106-43.eps figure 18 ii.7 - moire output the moire output is intented to correct a beat between horizontal video pixel period and actual crt pixel width. the moire signal is a combination of horizontal and vertical frequency signals. to achieve a moire cancellation, it has to be con- nected to any point on the chassis controlling the horizontal position. we recommend to introduce this horizontal controlled jitter on the relative ground of pll2 capacitor where this controlled jitter fre- quency type will directly affect the horizontal posi- tion.the amplitude of the signal is i 2 c adjustable. one point to notice is : - in case h-moire is not necessary in the applica- tion, h-moire output (pin 2) can be turned to as a 5 bits digital to analog converter output (0.3v to 2.2v v output voltage), - in case of no use in application, this pin must be left high impedance(or resistor to ground). h v moire h v moire odd frame even frame 9106-45.eps figure 20 : moire output waveform 23 ck d q q rst h-sync ck d q q monostable v-sync 9106-44.eps figure 19 : moire function block diagram TDA9106 23/30
iii - vertical part iii.1 - geometric corrections operating description (continued) the principle is represented in figure 21. starting from the vertical ramp, a parabola shaped current is generated for e/w correction, dynamic horizontal phase control correction, and vertical dynamic focus correction. the base of the parabola generator is an analog multiplier the output current of which is equal to : d i = k (v out - v dcout ) 2 where vout is the vertical output ramp, typically comprised between 2 and 5v, vdcout is the vertical dc output adjustable in the range 3.2v 3 3.8v in order to generate a dissymetric parabola if required (keystone adjustment). corner and corner balance corrections may be added to the e/w one. these are respectively 3rd and 2nd order waveforms. in order to keep a good screen geometry for any end user preferences adjustment we implemented the geometry tracking. due to large output stages voltage range (e/w, focus), the combination of tracking function with maximum vertical amplitude max or min vertical position and maximum gain on the dac control may lead to the output stages saturation. this must be avoided by limiting the output voltage by apro- priate i 2 c registers values. for e/wpart and dynamic horizontal phase control part, a sawtooth shaped differential current in the following form is generated : d i = k (v out - v dcout ) 2 then d i and d i are added together and converted into voltage for the e/w part. each of the four e/w components or the two dy- namic horizontal phase control ones may be inhib- ited by their own i 2 c select bit. the e/w parabola is available on pin 31 by the way of an emitter follower which has to be biased by an external resistor (10k w ). it can be dc coupled with external circuitry. the output connection of the vertical dynamic fo- cus is the same as the e/w one. this reverse parabola is available on pin 32. dynamic horizontal phase control current drives internally the h-position, moving the hfly position on the horizontal sawtooth in the range 2.8% th both on sidepin balance and parallelogram. ew output ew amp keystone corner corner balance sidepin amp parallelogram vertical dynamic focus output sidepin balance output current to horizontal phase vdcout vdcin 2 vdcout vdcout vmid vertical ramp v out vertical ramp v osc 31 32 9106-46.eps figure 21 : geometric corrections principle TDA9106 24/30
iii.2 - ew ewout = 2.5v + k1 (v out - v dcout ) 2 + k2 (v out - v dcout ) + k3 (v out - v dcout ) 2 |v osc - v mid | + k4 (v out - v dcout ) |v osc - v mid | v osc is the ramp pin 27 and v mid the middle of it, typically 3.5v k1 is adjustable by ew amplitude i 2 c register k2 is adjustable by keystone i 2 c register k3 is adjustable by cbow corner i 2 c register k4 is adjustable by spin corner i 2 c register iii.3 - dynamic horizontal phase control i out = k5 (v out - v dcout ) 2 + k6 (v out - v dcout ) k5 is adjustable by sidepin balance i 2 c register k6 is adjustable by parallelogram i 2 c register iii.4 - vertical dynamic focus vfoc out = 6v - 0.7 (v out - v dcout ) 2 no adjustment is available for this part except by means of tracking. iii.5 - vertical sawtooth generator the vertical part generates a fixed amplitude ramp which can be affected by s and c correction shape. then, the amplitude of this ramp is adjusted to drive an external power stage (see figure 22). the internal reference voltage used for the vertical part is available between pin 26 and pin 24. its typical value is : v 26 = v ref = 8v the charge of the external capacitor on pin 27 (vcap) generates a fixed amplitude ramp between the internal voltages, v l (v l = v ref /4) and v h (v h = 5/8 x v ref ). operating description (continued) 27 31 25 parabola generator oscillator 38 osc cap disch. h/hvin polarity sampling samp. cap vlow sawth. disch. ref transconductance amplifier charge current 29 vert_out vert_amp sub05/7bits vs_amp sub07/6bits cor_c sub08/6bits s correction c correction ew_amp sub09/6bits ew_out ew_cent sub0a/6bits spb_amp sub0d/6bits spb_out v_focus 32 paral sub0e/6bits corner corner sub0b/6bits corner balance sub0c/6bits internal signal to pll2 sync processor 33 1 vsyncin s/g 9106-47.eps figure 22 : vertical part block diagram TDA9106 25/30
when the synchronization pulse is not present, an internal current source sets the free running fre- quency. for an external capacitor, c osc = 150nf, the typical free running frequency is 106hz. typical free running frequency can be calculated by : f 0 ( hz ) = 1.6 e - 5 1 c osc a negative or positive ttl level pulse applied on pin 33 (vsync) as well as a ttl composite sync on pin 38 or a sync on green signal on pin 1 can synchronise the ramp in the range [fmin , fmax]. this frequency range depends on the external capacitor connected on pin 27. a capacitor in the range [150nf, 220nf] 5% is recommanded for application in the following range : 50hz to 120hz. typical maximum and minimum frequency, at 25 o c and without any correction (s correction or c cor- rection), can be calculated by : f (max.) = 2.5 x f 0 and f (min.) = 0.33 x f 0 if s or c corrections are applied, these values are slighty affected. if a synchronization pulse is applied, the internal oscillator is automaticaly synchronized but the am- plitude is no more constant. an internal correction is activated to adjust it in less than a half a second : the highest point of the ramp (pin 27) is sampled on the sampling capacitor connected on pin 25 at each clock pulse and a transconductance amplifier generates the charge current of the capacitor. the ramp amplitude becomes again constant and fre- quency independant. the read status register enables to have the verti- cal lock-unlock and the vertical sync polarity in- formations. it is recommanded to use a agc capacitor with low leakage current. a value lower than 100na is man- datory. good stability of the internal closed loop is reached by a 470nf 5% capacitor value on pin 25 (vagc). pin 30, vfly is the vertical flyback input used to generate the vertical blanking signal on pin 23. if vfly is not used, (v ref - 0.5), at minimum, must be connected to this input. in such case, the vertical blanking output will be activated by the vertical sync input signal and re- setted by the end of vertical sawtooth discharging pulse. iii.6 - i 2 c control adjustments then, s and c correction shapes can be added to this ramp. this frequency independent s and c corrections are generated internally. their ampli- tude are adjustable by their respective i 2 c register. they can also be inhibited by their select bit. at the end, the amplitude of this s and c corrected ramp can be adjusted by the vertical ramp ampli- tude control register. the adjusted ramp is available on pin 29 (v out ) to drive an external power stage. the gain of this stage is typically 25% depending on its register value. the dc value of this ramp is kept constant in the frequency range, for any correction applied on it. its typical value is v mid = 7/16 v ref . a dc voltage is available on pin 28 (vdcout). it is driven by its own i 2 c register (vertical position). its value is v dcout = 7/16 v ref 300mv. so the v dcout voltage is correlated with dc value of v out . it increases the accuracy when tempera- ture varies. iii.7 - basic equations in first approximation, the amplitude of the ramp on pin 29 (vout) is : v out - v mid = (v osc - v mid ) (1 + 0.25 (v amp )) with v mid = 7/16 v ref ; typically 3.5v, the middle value of the ramp on pin 27 v osc = v 27 , ramp with fixed amplitude v amp is -1 for minimum vertical amplitude register value and +1 for maximum on pin 28 (v dcout ), the voltage (in volts) is calcu- lated by : v dcout = v mid + 0.3 (vpos) with vpos equals -1 for minimum vertical position register value and +1 for maximum the current available on pin 27 is : i osc = 3 8 v ref c osc f with c osc : capacitor connected on pin 27 f : synchronization frequency operating description (continued) TDA9106 26/30
7 1 5 3 6 2 4 -12v c8 100nf c10 470 m f r5 5.6k w c1 220nf r3 1.5 w 1 2 3 j18 r11 220 w 1/2w r4 1 w 1/2w tp7 c18 100 m f 36v tp8 v yoke c41 470pf ic1 tda8172 r2 5.6k w r1 12k w r16 15k w r32 4.7k w d2 1n4148 c9 100nf c14 470 m f 1n4004 d1 1 j3 j2 +12v -12v 1 vertical deflection stage 100nf r40 12k w c4 vref j10 tp12 tp11 17 18 19 26 27 28 29 30 36 37 38 40 22 23 24 31 32 33 34 35 25 39 1 2 3 4 5 6 7 8 9 10 16 11 12 13 14 15 41 42 1 2 3 4 5 6 7 8 9 10 16 11 12 13 14 15 +12v ta1 ta2 cda ia ia qa qa gnd qb qb ib ib cdb tb2 tb1 v cc icc1 - mc14528 cc3 +12v 47pf +12v cc1 100nf cc2 10 m f cc4 47pf pc1 47k w c31 4.7 m f c13 10nf r36 1.8k w 20 21 sync/g gndd moire sda scl pllinh pll2c +5v h/hvin href hfly hlockout hgnd hout vsyncout fc2 fc1 c0 test vsyncin r0 v_focus pll1f hlockcap ewout vfly vout vdcout hpos xrayin h_focusc vcap vref h_focus v cc vagccap vgnd gnd v_blkout h_blkout houtem houtcol c16 220pf c23 47nf tp10 c6 100nf c5 100 m f +12v v_focus tp16 tp17 j12 r28 10k w vsync j11 hsync tp1 tp17 c32 100nf c30 100 m f +5v l1 10 m h tp5 c12 150nf c15 470nf c3 47 m f c2 100nf vref c17 220nf c29 1 m f c34 820pf tp9 tp15 r20 r44 10k w 10 w jp1 c7 22nf c27 47 m f c33 100nf href c21 47nf c28 820pf 5% r23 6.49k w 1% c44 10pf c26 1 m f r22 1.5k w r48 1k w r24 10k w r45 33k w r7 10k w r25 1k w r45 33k w v_focus tp14 xrayin 1 1 j9 j7 dynamic focus r8 10k w c22 33pf r10 10k w c25 33pf 1 j8 hfly r35 10k w tp2 tp8 r27 3.9k w r21 3.9k w +12v hblk vblk ic2 TDA9106 1 2 3 4 5 6 7 8 9 10 11 12 16 13 14 15 22 23 24 17 18 19 20 21 pwm7 test xtalout v dd ic3 - stv9422 xtalin b pwm6 pwm0 pwm1 pwm2 pwm3 pwm5 pwm4 scl sda rst gnd r g fblk vsync hsync pxck ckout +5v c45 10 m f +5v l2 10 m h c43 47 m f x1 8mhz c7 33pf c7 33pf r39 4.7k w r29 4.7k w r42 100 w r41 100 w c39 22pf c40 22pf +5v 4 3 2 1 j14 1 j15 +5v 1 j16 r49 22k w l3 10 m h +12v r13 1k w c20 1 m f r6 10 w c35 100nf r14 22k w q5 bc547 q4 bc557 c24 1nf r12 560 w c19 100 m f 63v t1 g5676-00 r47 82 w 3w 1 2 3 j17 +24v hdrive tp3 tp4 1 j6 horizontal driver stage 1 j1 r38 2.2 w 1w q3 tip122 c11 220pf r19 270k w r17 270k w r18 39k w q2 q1 r15 1k w r9 470 w r33 4.7k w r37 27k w bc557 +12v r31 27k w c36 1 m f r34 1k w e/w power stage r30 10k w 1 j13 r43 10k w c42 1 m f tilt e/w +12v pc2 47k w q6 std 5n20 9106-48.eps figure 23 : demonstration board application diagrams TDA9106 27/30
application diagrams (continued) 9106-49.eps figure 24 : pcb layout TDA9106 28/30
application diagrams (continued) 9106-50.eps figure 25 : components layout TDA9106 29/30
a1 b e b1 d 22 21 42 1 la e1 a2 c e1 e e2 gage plane .015 0,38 e2 e3 e sdip42 pmsdip42.eps package mechanical data 42 pins - plastic shrink dip dimensions millimeters inches min. typ. max. min. typ. max. a 5.08 0.200 a1 0.51 0.020 a2 3.05 3.81 4.57 0.120 0.150 0.180 b 0.38 0.46 0.56 0.0149 0.0181 0.0220 b1 0.89 1.02 1.14 0.035 0.040 0.045 c 0.23 0.25 0.38 0.0090 0.0098 0.0150 d 36.58 36.83 37.08 1.440 1.450 1.460 e 15.24 16.00 0.60 0.629 e1 12.70 13.72 14.48 0.50 0.540 0.570 e 1.778 0.070 e1 15.24 0.60 e2 18.54 0.730 e3 1.52 0.060 l 2.54 3.30 3.56 0.10 0.130 0.140 sdip42.tbl information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no licence is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectroni cs. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in lif e support devices or systems without express written approval of sgs-thomson microelectronics. ? 1997 sgs-thomson microelectronics - all rights reserved purchase of i 2 c components of sgs-thomson microelectronics, conveys a license under the philips i 2 c patent. rights to use these components in a i 2 c system, is granted provided that the system conforms to the i 2 c standard specifications as defined by philips. sgs-thomson microelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - morocco the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. TDA9106 30/30

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